The present invention relates to the known good integrated circuits, semiconductors in general and, more specifically, to improved Known Good Die (KGD) integrated circuit semiconductor devices which include memory components such as static RAM or dynamic RAM. This invention also relates to logic or application specific integrated circuits (ASIC).
Recent improvements to VLSI integrated circuit testing at the wafer level indicate that traditional test methods may not be optimal. Specifically, module level screens, such as time and resource consuming burn-in, temperature cycling, etc., are no longer unique in their ability to identify and eliminate latent defects.
It is well established within the test. industry that a high quality screen at the earliest point of assembly (i.e. wafer test) is typically,.economically optimal. It has been estimated that the cost of identifying and replacing defective die increase ten-fold at each level of packaging. Considering that the test cost alone can represent up to 50% of the product cost, high quality early screening, can represent a major savings. Effective die screening is especially important for Multichip Module (MCM) testing, where the ultimate MCM assembly yield is exponentially proportional to post wafer level test quality level. This fact alone may be why today""s MCMs are typically populated with relatively low number of die (2 to 10). When the number of dies exceeds 10, quality levels for individual die must be well above 99% to achieve acceptable MCM yields.
Many screening options are simply not available. during wafer test. These include at-speed test, temperature testing, and testing input/outputs at worst case voltage swings. Additionally, the module level has traditionally been the first level at which reliability-oriented screens such as burn-in can be performed. It is clear that relying on such a screen at the MCM level to first identify an unreliable die poses an unacceptably high risk of unacceptable yields to the MCM manufacturer.
To address this problem, the concept of Known Good Die (KGD) was developed. This was an industry/government initiative to develop test methodologies that allowed bare die to be screened to quality levels equivalent to those quality levels available at the module level. Guidelines for insuring Known-Good-Die (KGD) in JPL Space Flight Hardware published by the Electronics Parts Engineering Office 507, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, Calif. 91109, D-16389, Mar. 15, 1999 describes the concept of KGD and is herein incorporated by reference. KGD""s provide the highest reliability and minimum risk levels. Initially the prime method of achieving this goal was to develop temporary die attach methods which permitted module level testing and screening (e.g.) burn-in to be performed prior to die classification. Over time, however, the disadvantage of this mechanical-packaging oriented approach has become evident. It has been proven to be difficult to implement a contacting approach that can maintain a reliable. electrical contact during the rigors of burn-in, and temperature extreme testing, while not damaging the die pad surface (thus reducing the likelihood of defect free bonding during subsequent module assembly). Carriers that are capable of this delicate balance tend to either be prohibitively expensive and/or not sufficiently durable for production manufacturing. Often the cost associated with temporary attachment exceeds the cost associated with simply placing wafer level screened die directly on the MCM.
The state of the art in this area indicates that a goal of wafer-level screening is achievable. First, novel test methods have been developed for CMOS. which have been shown to enhance product reliability. These methods are used to identify defects in dies. These include quiescent current (Iddq) testing, which was originally proposed in 1981. This test method provides improved detection of bridging faults as compared to standard (i.e. stuck fault). test methods and die defects. Subsequent MCM infant mortality is, therefore, reduced. Iddq testing was subsequently shown to reduce burn-in failures by 51%. The Iddq test is used primarily to detect shorts in the circuit. If Iddq exceeds a limit, it is presumed that there are metal or conductor lines that have a short. circuit or a piece of conducting foreign material shorting two lines. If a part should be drawing a nannoamp or a microamp, and it is drawing 100 microamps, the part is obviously defective.
A defect activating stress test method can be the application of an elevated voltage (Vdd) for a specified period of time, especially when followed by Iddq tests. This approach takes advantage of failure mechanism acceleration factors associated with higher supply voltages. Another defect detecting test method is Very Low Voltage Testing, where tests are conducted at supply voltages close to the transistor threshold voltage. By targeting defects that induce internal voltages that are not full Vdd transitions, this methodology has the potential for detecting a variety of subtle malfunctions that could ultimately evolve into failures.
While alternative testing exists, what still remains is to select and implement the correct die test methods, given the specific attributes of the semiconductor. Each semiconductor manufacturing facility""s process has its own unique defect densities and potential reliability risks. This is especially true for facilities which fabricate radiation hardened Integrated Circuits (ICs.) because these processes tend to display unique (as compared to commercial ICs) features. Additionally, given the nature of the radiation hardened ICs, high reliability is a paramount concern.
Extending successful Application Specific Integrated Circuit (ASIC) Known Good Die (KGD) approaches to Static Random Access Memories (SRAMs) is not without challenges. For instance, SRAMs display different temperature sensitivities than ASICs. SRAMs are adversely affected by both hot and cold temperatures. Cold temperature testing is not typically possible during a wafer test, because due to condensation, etc., the test chuck can raise the temperature during testing. Reducing the temperature from room temperature is, therefore, not feasible precluding the ability to verify performance under entire operating conditions. Another SRAM specific problem results from the use of redundancy to improve die yields. As standard manufacturing practice, additional memory cells are added to the SRAM. If during testing, defective memory cells are found, these cells are logically disconnected and replaced with these excess cells. These defective cells can continue to elevate the die quiescent current (Iddq) while not affecting functionality. This then complicates Iddq testing, which is an essential element of Known Good Die testing. The presence of analog circuitry within the sense amplifiers, which can elevate the quiescent current of defect-free devices so that the additional contribution of a defect cannot be detected, is also an element unique to memories which must be addressed.
Additionally large capacity static RAM cannot be tested utilizing standard Iddq testing. The reason is that static RAM may include millions of memory cells, each contributing to the sum total of Iddq. Therefore, a short or failure which would elevate the Iddq by 1 to 200 microamps is hot detectable when the defect free Iddq can be in the order of 2 milliamps.
The term multi-pattern data retention test as used in this application refers to placement of a pattern of logical ones and zeros in a device such as a memory or a logic circuit where there are ones and zeros physically adjacent to each other. The pattern may be a checkerboard or checkerboard bar as illustrated in FIGS. 4 and 5 or any other arbitrary pattern. The test preferably uses at least a pattern and its compliment such as checkerboard and checkerboard bar. In its simplest form, the test can be conducted by reading out the information in memory after a predetermined time and comparing the results which will identify cells which leak charge. In another embodiment, a defect detecting test, such as a drop in Vdd, may be conducted while a pattern is in memory to stress the device prior to reading out the memory. In all cases, memory input and memory output are compared to determine if data is accurately retained in the memory. The test identifies intra-cell leakage by charging adjacent cells to high and low states which allows leakage of charge.
Use of two complimentary patterns provides an opportunity for charge to leak from one cell to an adjacent cell in either direction. This use of two or more patterns increases the reliability of the test results.
In one embodiment of this invention there is provided a method for screening for a Known Good Die comprising conducting a multi-pattern data retention test on a memory located on a die and classifying as a Known Good Die if criteria for the multi-pattern data testing is met. This method further comprises testing of the ability to retain stored data at voltages less then designed operating voltages. One or more test patterns are placed in a memory and the data is read out and compared to the original data to determine if any data has been lost. The multi-pattern data retention test identifies intra-cell leakage.
In another embodiment the multi-pattern data retention test comprises recording patterns of data in a memory, reading out of the data recorded in the memory after a period of time and comparing recorded data and read out data to determine data retention.
In another embodiment the multi-pattern data retention test comprises writing a pattern at Vdd, lowering Vdd, restoring to the writing Vdd, reading the memory, comparing the written pattern to a pattern obtained when reading the memory, determining of data retention and repeating the above procedure for different patterns.
In another embodiment this invention comprises conducting a defect activating test on a functionally good die; conducting a die screening test after conducting the defect activating test; analyzing data from said die screen test to determine changes of measurements; analyzing of changes of measurements to determine if a stability objective is met; classifying as a Known Good Die if a change of measurement stability objective has been met and when the stability objective is not met, returning to the defective activating screen test and repeating each subsequent procedure. A functionally good die is defined as a device which is functioning properly at specified operating voltage (Vdd), current, and/or temperatures. A functionally good die operates as specified at a specified Vdd. The defect detecting test may be a high voltage stress test, a thermal cycling test, or a comparison of multi-pattern data retention tests. Defect activation is a test where a latent defect in a die is activated by a condition such as an excessive Vdd (overvoltage stress).
In another embodiment a method for screening for a Known Good Die comprises conducting a first multi-pattern data retention test; subjecting the die to a defect activating test; conducting a second multi-pattern data retention test and comparing the results to the first multi-pattern data retention test to determine if defects have been activated; and determining if a multi-pattern data retention test stability objective has been met.
In another embodiment there is a method for screening for a Known Good Die which is dependent upon changes in measurement from test to test. The method comprises conducting a defect activating test on a functionally good die, conducting a screening test after conducting the defect activating test, analyzing data from the die screen test to determine changes of measurement, analyzing of measurements to determine if a stability objective is met and classifying as a Known Good Die if a change of measurement stability objective has been met. In this method high voltage defect activating tests are typically used.
This invention relates to development of wafer level testing that will screen out defective die that would otherwise not be eliminated until the subsequent module (MCM) level screens. Recent improvements in wafer level test methods make such testing possible. It is necessary to perform a defect-oriented analysis of the MCM screens. Rather than deploying a brute force approach of simply subjecting the die to the same screens that would be applied at the module level, defect-oriented analysis concentrates instead on identifying exactly what defects are being identified during these MCM module screens. Once the defect-oriented analysis is established, one can then select and/or develop test methods which target and eliminate dies having specific manufacturing flaws. This produces an equivalent MCM screen by defect-oriented testing at the die level.
This invention detects and screens defects in memory devices, by using the architecture and function of memory circuits and how they differ from logic devices. A many-million SRAM memory device has too much leakage from redundancy implementation and inherent cell leakage. This high background leakage overwhelms any defect-related leakage, rendering Iddq testing useless. This invention replaces Iddq testing in the logic KGD flow (Iddq-high voltage-Iddq) with a multi-pattern data retention test (as seen in FIG. 2).
With this invention, Iddq testing for SRAMs has been discarded and the concept of multi-pattern data retention testing has been used. The multi-pattern data retention allows inspection of each cell for cell leakage and block-to-block leakage, etc. Block-to-block leakage is defined as leakage from one memory area or block to another. A block may have thousands of cells. Still further, the multi-pattern testing will immediately reveal shorts in bit lines or word lines because the pattern will be disrupted. The disruption is especially noticed when an inverse of a pattern or a pattern-bar is used.
This multi-pattern data retention SRAM test is similar to defect detection used for logic Iddq testing (but not to prior art SRAM testing). Multi-pattern data retention testing is the testing of memory device""s ability to retain stored data at very low voltages. The memory may be SRAM or Dynamic RAM (DRAM). If a defect is present, then the defect-induced leakage will degrade the stored data signal resulting in loss of data. The technique must be multi-patterned to detect leakage in the xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d states, cell to cell, block to block, high voltage to low voltage, etc. to detect defective leakage which can be detected by alternate-line biasing. If a conductive defect is across a pair of signal lines, the defect and associated leakage can only be detected if there is a bias across the defect, and the associated line pair.
There are two different ways to conduct a multi-pattern data retention test. One is merely to lower the Vdd voltage and determine if it is possible to read and write at the lower voltages. The second way is to write a pattern at normal Vdd, drop the Vdd to a lower level, bring the device back to normal operating voltage, read the memory and determine if the memory has failed to read out all data recorded therein.
Multi-pattern data retention testing uses different patterns which allow various combinations and permutations of charge and no charge (ones and zeros) from cell to cell. This is especially important because if two cells side by side each are charged to Vdd volts, there may be no place for the voltage to leak to. There can be no inter-node leakage or inter-line leakage in such a situation. It is for this reason that alternately written cells provide a powerful tool for memory testing.
This multi-pattern memory data retention test overcomes the limitations of standard Iddq testing by ignoring total chip Iddq (leakage) and focusing on the purpose of the memory device. This allows for detailed screening of each memory element and the associated architecture. By combining a multi-pattern data retention test with a defect activation screen, such as high voltage performed on the element, a highly effective Known Good Die screen for memory devices is provided.
A method of providing a higher level of Known Good Die (logic or memory) is to monitor changes of measurements through a series of defect activating tests such as voltage screens or thermal cycling and determine if parametric instabilities exist. Changes of measurements are defined as changes in currents, memory retention or other operating parameters which occur from one test to the next in a series of iterative tests. For example, constantly increasing leakage currents can be a sign of future failures, while an asymptotic behavior may indicate stability. This allows for the activation and detection of more subtle defects not seen during one-pass testing. This produces a more reliable product.
While this invention provides an opportunity to enhance the standard manufacturing test strategy for single chip modules, it can be a major development for Multichip Modules (MCMs). Such improvements can improve-packaging assembly, screening, and second level assembly yields, dramatically reducing costs. Additionally, overall product failure rates can potentially be reduced, thereby improving system and life cycle costs, minimizing program delays and cost associated with component fails late within system integration.